Typically, a memory device that stores data is largely classified as either a volatile semiconductor memory device or a nonvolatile semiconductor memory device. The volatile memory device principally represented as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory), etc. is fast with regard to the input/output operation of data, but has a shortcoming in that stored contents are lost when a power supply is stopped. The nonvolatile memory device principally represented as EPROM (Erasable Programmable Read Only Memory) or EEPROM (Electrically Erasable Programmable Read Only Memory) etc., on the other hand, is slow with regard to the input/output operation of data, but has the benefit of maintaining intact the stored data even when a power supply is interrupted.
A conventional memory device commonly employs a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) based on MOS (Metal Oxide Semiconductor) technology. For example, a stack gate-type transistor memory device of a stack structure adapted on a semiconductor substrate formed of silicon material, and a transistor memory device of a trench gate-type having a structure buried in the semiconductor substrate, are under development. However, a width and length of the channel in the MOSFET must be formed with a sufficient minimum required length in order to suppress a short-channel effect. Further, a thickness of a gate insulation layer formed between a gate electrode formed on the channel and the semiconductor substrate must be extremely thin. Due to these fundamental problems, it is difficult to realize a memory device of a nano-level ultra microstructure for the MOSFET.
Memory devices are being researched to replace the MOSFET described above with new devices that do not experience the abovementioned undesirable characteristics. Micro electro-mechanical system (MEMS) and nano electro-mechanical system (NEMS) technology applied to suspend bridge memory (SBM) are becoming an issue. One such nonvolatile memory device using the MEMS technology is disclosed in U.S. Pat. No. 6,054,745, incorporated herein by reference in its entirety.
FIG. 1 is a schematic sectional view of a memory device according to a conventional art.
As shown in FIG. 1, a conventional memory device is obtained by forming an FET (Field Effect Transistor) sensor 221, attractive electrode part 223, and cantilever electrode supporter 225, which are distinguished from one another, on a shallow trench isolation (STI) layer 224 formed on a substrate. The FET sensor 221 comprises a polysilicon gate electrode 230 and a source/drain region 227. A cantilever electrode 240 is also formed such that one side of the cantilever electrode 240 is supported by, and electrically connected to, the cantilever electrode supporter 225, wherein the cantilever electrode 240 is distanced by a predetermined height from the attractive electrode part 223 and the FET sensor 221. The cantilever electrode 240 can be curved toward the attractive electrode 232 by an electric field induced by the attractive electrode part 223. Then, even when the electric field induced by the attractive electrode part 223 is eliminated, the cantilever electrode 240 can maintain its curved state by an electric field induced from electrons held by a polysilicon gate electrode 230 of the FET sensor 221. For example, the polysilicon gate electrode 230 corresponds to a floating electrode of a flash memory device, for capturing electrons tunneled through a tunnel oxide layer that is formed of a dielectric formed on a source-drain region 227 of the FET sensor 221. The attractive electrode part 223 and the cantilever electrode supporter 225 are formed of the same polysilicon material 232 as the polysilicon gate electrode 230. The elements under attractive electrode part 223 and the cantilever electrode supporter 225, respectively, are fabricated to be co-planar with each other in the same process, for example, as disclosed in U.S. Pat. No. 6,054,749, incorporated herein in its entirety by reference. The cantilever electrode 240 is also formed of polysilicon material in the cantilever electrode supporter 225.
That is, in a conventional memory device, a nonvolatile memory device can include an attractive electrode 232 for curving the cantilever electrode 240 by an electromagnetic force, and an FET sensor 221 including the gate electrode 230 for maintaining the curved state of the cantilever electrode 240, in a lower part of the cantilever electrode 240.
However, a conventional memory device and method of manufacturing the same such as that shown in FIG. 1 have the following problems.
In the conventional memory device and method of manufacturing the same, attractive electrode part 223 and FET sensor 221 are adapted on the same horizontal position, and the cantilever electrode 240 should have a sufficient length to cover the attractive electrode part 223 and the FET sensor 221 in an upper part of the attractive electrode part 223 and the FET sensor 221, thus there is a shortcoming of decreasing an integrated level of memory devices.
Further, in the conventional memory device and method of manufacturing the same, it is difficult to form the cantilever electrode 240 to be positioned suspended above a void in an upper portion of the attractive electrode part 223 and FET sensor 221 by a microstructure of a given length and line width, and so a yield decreases.
Further, in the conventional memory device and method of manufacturing the same, only 1 bit of data is programmed or read out for each unit cell comprising the cantilever electrode 240, attractive electrode 232, and FET sensor 221, and thus, it is difficult to store multibit data.